EDN

Power-aware FPGA design (Part 2)

FPGAs offer several embedded RAM blocks with unique sizes but variable aspect ratios. This feature opens the door for different cascading schemes. Fig 9 is an illustration of two alternatives that ...
EDN

ISLA11xP50 Output Data Timing and Synchronization

This application note describes the ISLA11xP50 analog-to-digital converter (ADC). The purpose of this paper is to provide fundamental information on the output data timing and synchronization ...
Semiconductor Engineering

Rapid Timing Constraints Signoff With Automated Constraint Management

Signoff of a system on chip (SoC) or IP design has multiple aspects, but often timing closure is the most challenging. Early use of a static timing analysis (STA) tool is clearly important, and such a ...
Design-Reuse

Achieving FPGA Design Performance Quickly

This column highlights the broad steps designers need to complete as they close timing and how tool automation helps to simplify the process. Today's engineering teams are tasked with delivering ...
Design-Reuse

Actel's Libero IDE Delivers Unmatched Value, Flexibility and Efficiency for Complex FPGA-Based Designs

New Static Timing Analysis Engine and Expanded Third-Party Support Enable Designers to Meet Timing Closure and Achieve Higher Performance MOUNTAIN VIEW, Calif., July ...
Embedded

FPGA Clock Schemes

One of the most important steps in the design process is to identify how many different clocks to use and how to route them. This article tells you how to use routing resources efficiently.