It is well known that the task of verification looms large in the design of digital IP, as well as the design of SoCs. The target is to reach 100% for both RTL code and functional coverage, minimizing ...

Multi-million gate system-on-a–chip (SoC) designs easily fit into today’s FPGAs. Due to the ever increasing demand for more speed, less area, and less power, the transformation of a customer’s RTL ...

In recent years, many longstanding assumptions about formal verification have been rendered obsolete by ever-improving technology. Applications such as connectivity checking have shown that formal can ...

VC Formal Datapath Validation application delivers over 100X speed-up in formal verification between a reference C/C++ algorithm and RTL design implementation over conventional techniques The new app ...

Reset architectures are notoriously complex and difficult to verify. Today’s SoCs contain highly complex reset distributions and synchronization circuitry. Often, reset trees can be larger than clock ...

Traditionally, formal verification is used after the fact for bug hunting or design-rule checking. It has yet to be applied up front, where it would affect design decisions at the RTL coding stage.

Central to Conquest MAI is its ability to infer functional intent directly from RTL to automatically identify SFCs such as FSMs, FIFOs, counters, shifters, and memory. It analyzes logic behavior to ...

Intended Design Behavior Is Captured and Preserved, Reducing Life Cycle Design Costs and Verification Time While Enabling Efficient Knowledge Transfer and Design Reuse MOUNTAIN VIEW, Calif. -- January ...

More processors on SoCs means more sophisticated cache control. This article describes formal techniques for verifying cache coherency for the ARM AMBA AXI Coherency Extensions (ACE) protocol. Fig 1.

MUNICH, GERMANY –– February 11, 2013 –– OneSpin Solutions™ (www.onespin-solutions.com), provider of innovative formal assertion-based verification (ABV) solutions, announced immediate ...