EDN

Recycle RTL test benches to verify Transaction-Level IP Models

System architects working on system-on-chip (SoC) designs are hampered by the dearth of reliable ways to evaluate an architecture or verify hardware and software together. Fortunately, SystemC, an ...
EDN

Legacy RTL brought into system-level flow

As system-on-chip complexity grows, designers are turning to electronic system-level (ESL) methodologies to create next-generation designs. Designers might hesitate to use ESL because of legacy RTL ...
Business Insider

Mentor Graphics Expands Formal Verification's Reach with New Cross-Platform GUI and Apps for Sequential Logic Equivalence Checking and CDC Gate-Level Analysis

WILSONVILLE, Ore., April 20, 2017 /PRNewswire/ -- Mentor, a Siemens business, today announced new formal-based technologies in the Questa Verification Solution that provide RTL designers and ...
Electronic Design

Predictive-Analysis Tool Sniffs Out Gate-Level Problems In RTL Code

Thanks to a fast, built-in synthesis engine, Atrenta's SpyGlass 3.0 predictive-analysis tool detects very complex structural problems in register transfer level (RTL) code that would otherwise only ...